Thanks for the reply, but last night I was able to get the code sorta working- part of my problem was that the slave wasn't latching to the falling edge of the CS line- you can see in my slave code that inside the while(1) loop, it effectively says if (!CS), send 128 bytes. I had hoped that this line: while (IFG2 & UCB0TXIFG == 0); // Wait for TX buffer to clear would cause the MCU to wait for a new set of 8 clock pulses from the master before incrementing "j" and sending the next byte, but apparently the TX buffer can be cleared even if the byte has not been clocked out of the shift register, I guess. So I changed the code to set a "ready" flag high if CS is high. If CS is low AND the flag is high, the code sets the flag low and transmits a single byte. This method works, but two things- first, I'm still occasionally getting byte errors- once every 100 or so bytes, a byte will be duplicated, (e.g. ...89, 90, 91, 91, 92...) and second, this kind of defeats the purpose of using a clock signal to trigger transmission because I have to cycle the CS line every time I want to send a single byte. I tried sending the entire 128 bytes after a latch, but I got the same garbled mess that I was getting previously. Here is the relevant part of the updated slave code followed by the relevant part of the master code. Thanks again Slave: while(1) { if (P2IN & 0x02) // Wait for Chip select { UCB0CTL1 |= UCSWRST; ready = 1; } else { if (ready) { ready = 0; UCB0CTL1 &= ~UCSWRST; // Enable SPI write_byte0(j); // Write a single byte j++; if (j == 127) j = 0; } } } Master: void main( void ) { WDTCTL = WDTPW + WDTHOLD; __bis_SR_register(GIE); // General interrupt enable initialize_clocks(); initialize_SPI(); initialize_pins(); while(1) { for (int j = 0; j < 128; j++) { P4OUT |= 0x01; // Deselect slave __delay_cycles (50); // Delay 1 ms P4OUT &= ~0x01; // Select slave __delay_cycles (50); // Delay 1 ms AFC_data[j] = write_byte1(j); // Send a byte of data __delay_cycles (50); // Delay 1 ms } } }
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