Hi, looks like your running not from your LF crystal connected to XT1 but from the REFO which is the safety clock for ACLK. Did you cleared the OFIFG and checked if the LFOIFG is cleared as well. Please check code examples of F5528 but here is in principle what you need: do { UCSCTL7 &= ~(XT1LFOFFG + DCOFFG); // Clear XT1 & DCO fault flags SFRIFG1 &= ~OFIFG; // Clear OSC Fault flag for (i = 0x0FFF; i > 0; i--); // Time for flag to set???? P1OUT ^= BIT0; // Toggle P1.0 }while ( (SFRIFG1 & OFIFG) ); Please also check the user's guide 5.2.12 UCS Module Fail-Safe Operation. Also please take care that you consider the parasitic caps of your PCB when you setup the capacitive load for your crystal. The best is to measure it witha coutner and align the cap setting to have the value closest to 32768 Hz. Or you measure the parastic caps with and LC meter. Best regards, Dietmar
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