TXIFG is the "gatekeeper" for a two-byte FIFO that sits in front of the SPI Tx (MOSI) wire. It is set when there are at least 8 (of the 16) bits available to put a byte into. When your 3-byte sequence is finished, there are still (roughly) 12 bits left in the FIFO. SPI by definition receives simultaneously with transmitting, even if what is received is worthless. The key is that once one byte is received (RXIFG), you know that one byte has been (completely) transmitted. Once you count 3 bytes received, you are finished and can de-assert /CS. To use RXIFG you do need to read (and throw away) the Rx byte ("(void)UCB0RXBUF;") UCBUSY indicates whether the FIFO is non-empty, so you could also wait for it to go low.
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