Hello All, I am having issues on both the MSP430FR5989 and MSP430FR6989 in using the SPI on USCI A0. First off, I am configuring it for 3-wire Master mode to talk with an external sensor. The issue I am having is that I can transmit data and see it while monitoring the SIMO line, however when I monitor the clock line, I see no activity, and furthermore, I do not get any RX interrupts. Here is the code I have been running (simplified to try and debug the SPI issue). Note, ,there may be many inefficiencies in the code. I don't care I am just trying to get the SPI to work first. int main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer // Disable the GPIO power-on default high-impedance mode to activate // previously configured port settings PM5CTL0 &= ~LOCKLPM5; // Configure one FRAM waitstate as required by the device datasheet for MCLK // operation beyond 8MHz _before_ configuring the clock system. FRCTL0 = FRCTLPW | NWAITS_1; // Clock System Setup PJSEL1 &= ~BIT4; PJSEL0 |= BIT4; CSCTL0_H = CSKEY >> 8; // Unlock CS registers CSCTL1 = DCOFSEL_4 | DCORSEL; // Set DCO to 16MHz CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; // Set SMCLK = MCLK = DCO, // ACLK = LFXTCLK (Note, on development baord, it was found to be 37.2 kHz) CSCTL3 = DIVA__1 | DIVS__2 | DIVM__1; // Set all dividers CSCTL4 &= ~(LFXTBYPASS | LFXTOFF); // Ensure crystal not in bypass do { CSCTL5 &= ~LFXTOFFG; // Clear XT1 fault flag SFRIFG1 &= ~OFIFG; } while (SFRIFG1&OFIFG); // Test oscillator fault flag CSCTL0_H = 0; // Lock CS registers /* Setup USCA0 registers */ P2SEL0 |= (BIT0 | BIT1 | BIT2); P2SEL1 &= ~(BIT0 | BIT1 | BIT2); UCA0CTLW0 = UCSWRST; UCA0CTLW0 |= (UCCKPL | UCMSB | UCMST | UCSSEL__SMCLK); // This is VERY important to keep these settings! UCA0BRW = 0; UCA0CTLW0 &= ~UCSWRST; while (1) { UCA0IFG &= ~UCRXIFG; UCA0TXBUF = 0x5A; while (!(UCA0IFG & UCRXIFG)); } return 0; } Like I said, I do not get any receive interrupts, so the loop only executes once. If i change the while statement to look at the TX flag, then it runs infinitely.
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