Jose, I believe what Bruce is referring to is the fact that there are two interrupts in Timer A, as described in slau356, these are represented in the interrupt definitions as: TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ The _0 refers to matches in the CCR0 registers, the _N refers to any other match or TAIFG. So I was setting up timer A to fire on overflow, but I was enabling the interrupt for CCR0 match. My code now looks like this after some other changes: // **************************** // TIMER CONFIG // **************************** // - TimerA configuration __disable_irq(); TIMER_A0->CTL = TIMER_A_CTL_SSEL__SMCLK | TIMER_A_CTL_ID__8 | TIMER_A_CTL_MC__CONTINUOUS | TIMER_A_CTL_CLR | TIMER_A_CTL_IE; TIMER_A0->EX0 = TIMER_A_EX0_IDEX__8; NVIC_SetPriority(TA0_N_IRQn,1); NVIC_EnableIRQ(TA0_N_IRQn); __enable_irq();
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