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Forum Post: RE: MSP430F2471: Confirm the internal latency between CPU fetch and I/O execution.

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[quote user="Kaka"]I checked this by using MSP430 Launch Pad by outputting the MCLK on 1.4 and changing the P1.0 output with step execution on CCS. As a result , the I/O was changed the 3 cycles and MCLK was stopped on 5 cycles.[/quote] I do not understand your statements at all. From what I know, an output instruction consists of either 2 or 3 words and takes anywhere from 3 to 6 MCLKs to execute.For example, the machine code of the insturction MOV.B #BIT1,&P1OUT consists of t2 words, 43D2 and 0021 . With a MSP430 CPU. it takes 4 MCLKs to execute, whereas for MSP430 CPUX, it takes 3 MCLKs to execute. The word 43D2 is pre-fetched during the last MCLK of the previous instruction. The word 0021 is fetched during the first MCLK. The next instruction is pre-fetched during the last (3rd or 4th for CPUX or CPU respectively) MCLK of this instruction while the output appears during the MCLK prior to the last.

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