Forum Post: MSP432 COMP C1.0 input at Vcc

I'm trying to configure and MSP432 launchpad to use COMP to compare two separate signals. the problem I have is (P6.7)C1.0 remains at Vcc while (P6.6)C1.1 is adjustable the circuit for (P6.7)C1.0 is terminated by a 100K to GND to remove any parasitic charge, then to a 10Microfarad cap to decouple the DC, allowing the AC pulse to pass. C1.1 is a 10K POT to vary the level between VCC and GND I also use (P7.2) C1out to detect a change currently using CCS 6.1.3 When I measure the inputs C1.0 remains at VCC. I used the Circuit diagram in the specs, but believe the power reference is somehow still connected causing the input C1.0 to have a Vcc voltage. #include "msp.h" volatile unsigned int i; int main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop WDT // =========================================================== // GPIO Setup // =========================================================== P1DIR |= BIT0; // output led // COMP-1 inputs / C1OUT puts P6SELC |= BIT6 | BIT7; // Configure P6.7=C1.0 P6.6=C1.1 P7DIR |= BIT2; // C1OUT set Dir P7SEL0 |= BIT2; // C1OUT follow input level of COMP1 // $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ // COMP1 trip the Photo Beam // $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ CE1CTL0 = CEIMEN | COMP_E_CTL0_IMSEL_1| CEIPEN | COMP_E_CTL0_IPSEL_0; // Enable V+ & V- CE1CTL1 = CEPWRMD_1; // normal power mode CE1CTL3 = 0xFFFC; // disable all ports except 0 & 1 CE1CTL1 |= CEON; // Turn On Comparator_E // #7=COMP1 NVIC_ISER0 |= INTISR7; __no_operation(); // For debugger __enable_interrupt(); while (1) { for (i = 20000; i > 0; i--); // kill some time P1OUT &= ~BIT0; // CLR led } } void COMP_E1_IRQHandler(void) { P1OUT |= BIT0; // on board RED led CE1IV = 0x00000000; // clr COMP-1 INT CE1INT &= ~(0x0013); // __no_operation(); // For debugger }