Forum Post: RE: What effects does debug under CCSv5 with SBW connections have on interrupt response?

Thanks to you both for replies. I upped clock to 8 MHz with no change in symptoms, and 'scope shows no noticeable difference in UART Tx data in CCS/SBW mode vs standalone. Processor is in LPM3 during UART activity and interrupts come at 44 uS rate (11 bits at 4 us each). The unpredictable behavior may be in the early-stage code for my receiving devices (up to 40 -F5131's along an RS485 bus). I'll start to work from that end Regardless, I'd be interested in an app note or some-such that indicates how the debug tool (MSP-FET430UIF) and SBW and JTAG each interact with the processor. I've always wondered how they may affect interrupts (or anything else)