Its been 5 days..... any progress? in particular I would like to know the details of what the actual inputs to the mux that drives the dma_trigger for a particular channel... there are 8 channels. Each channel has an 8-to-1 mux driving its dma_trigger. For each channel can you please tell me explicitly what each of the 8 inputs to the mux are You will need to go rattle the h/w engineers about this who will have to look at the internal dma wiring schematic.
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