We have recently taken some extensive measurements to characterize the MSP430 ADC to see if readings are within the expected tolerance. We used our target hardware for the characterization. The hardware uses the internal 2.5V reference for the ADC. One of the analog inputs was isolated from the signal on the board and instead driven directly from a bench power supply. We then swept the bench supply from 0 to 2.5V in 100mV increments. For each voltage, the numerical voltage output displayed on the bench supply was confirmed to be within 1mV of the displayed voltage using a DMM. We then graphed ADC Counts vs. input voltage as follows. The graph is linear with the expected differential variance around the ideal. So far so good, but things start to look odd when we really zoom in to a 1V window and sample at every 10mV. The next graph below charts error counts vs. expected (ideal) counts at each voltage input and this specifically what is concerning to us. I would expect the below response to be a horizontal line with a Gaussian distribution of +/- count errors about the line. Instead it exhibits large and fairly regular periodic jumps in the error count. With the 2.5V reference, the transfer function is ~610uV/bit. The total unadjusted error in the datasheet is 5 LSBs, so I’m presuming that means 5 counts, or 5 * 610uV ~ 3mV. Instead we are seeing variances amounting to > 60 counts for a 10mV change in the input voltage. So this is looking more like a ±2 5 = ±32 counts of non-random error instead of 5 counts. Can you please clarify/explain what we are seeing here? Note this response is fixed to this ADC. We’ve captured the identical characteristic on 3 of the other ADC inputs. We have not tried a second hardware sample yet. I will have my colleague who is working on this evaluate another board sample to see if the characteristic is similar. What is the best way to post the pictures? Adam We have recently taken some extensive measurements to characterize the MSP430 ADC to see if readings are within the expected tolerance. We used our target hardware for the characterization. The hardware uses the internal 2.5V reference for the ADC. One of the analog inputs was isolated from the signal on the board and instead driven directly from a bench power supply. We then swept the bench supply from 0 to 2.5V in 100mV increments. For each voltage, the numerical voltage output displayed on the bench supply was confirmed to be within 1mV of the displayed voltage using a DMM. We then graphed ADC Counts vs. input voltage as follows. The graph is linear with the expected differential variance around the ideal. So far so good, but things start to look odd when we really zoom in to a 1V window and sample at every 10mV. The next graph below charts error counts vs. expected (ideal) counts at each voltage input and this specifically what is concerning to us. I would expect the below response to be a horizontal line with a Gaussian distribution of +/- count errors about the line. Instead it exhibits large and fairly regular periodic jumps in the error count. With the 2.5V reference, the transfer function is ~610uV/bit. The total unadjusted error in the datasheet is 5 LSBs, so I’m presuming that means 5 counts, or 5 * 610uV ~ 3mV. Instead we are seeing variances amounting to > 60 counts for a 10mV change in the input voltage. So this is looking more like a ±2 5 = ±32 counts of non-random error instead of 5 counts. Can you please clarify/explain what we are seeing here? Note this response is fixed to this ADC. We’ve captured the identical characteristic on 3 of the other ADC inputs. We have not tried a second hardware sample yet. I will have my colleague who is working on this evaluate another board sample to see if the characteristic is similar.
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