1. Initial sequence for setting SMCLK with XT1 UCSCTL3 |= SELREF__XT1CLK + FLLREFDIV__1; UCSCTL0 = 0x0000; UCSCTL1 = DCORSEL_4; UCSCTL2 = FLLD_1 + 149; __bic_SR_register(SCG0); 2. Switching SMCLK source to XT2 UCSCTL6 &= ~XT2OFF; UCSCTL6 &= ~XT2DRIVE0; UCSCTL4 |= SELS__XT2CLK + SELM__XT2CLK; 3. Switching back the SMCLK source to XT1 UCSCTL6 |=XT2OFF; UCSCTL3 |= SELREF__XT1CLK + FLLREFDIV__1; UCSCTL0 = 0x0000; UCSCTL1 = DCORSEL_4; UCSCTL2 = FLLD_1 + 149; __bic_SR_register(SCG0);
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