Hello, i'm using a MSP430f5172 with SMCLK sourced from DCOCLK at 8Mhz. with the Debugger attached the serial communication works fine. As soon as the Debugger is deattached and LPM3 (but also other LPMs) is entered then i do not get all bytes received. If i disable LPM all works fine. USART configured as: #define ANT_PORT_DIR P1DIR #define ANT_PORT_SEL P1SEL #define ANT_PORT_OUT P1OUT #define ANT_PORT_REN P1REN #define ANT_PORT_IN P1IN #define ANT_RXD BIT1 #define ANT_TXD BIT2 #define ANT_RTS BIT3 #define ANT_SLEEP BIT4 #define ANT_RESET BIT5 // ANT RxD //ANT_PORT_DIR |= ANT_RXD; ANT_PORT_SEL |= ANT_RXD; // ANT TxD ANT_PORT_SEL |= ANT_TXD; // ANT RTS IN ANT_PORT_DIR &= ~ANT_RTS; ANT_PORT_REN |= ANT_RTS; ANT_PORT_OUT |= ANT_RTS; // ANT Sleep out default sleep ANT_PORT_DIR |= ANT_SLEEP; ANT_PORT_OUT |= ANT_SLEEP; // ANT reset default hold in Reset ANT_PORT_DIR |= ANT_RESET; ANT_PORT_OUT &= ~ANT_RESET; ANT_PORT_OUT |= ANT_RESET; UCA0CTL1 |= UCSWRST; // **Initialize USCI state machine** UCA0CTL1 |= UCSSEL_2; // SMCLK UCA0BR0 = 0x8A; // 8MHz 57600 UCA0BR1 = 0x00; // 8MHz 57600 //UBR00=0x8A; UBR10=0x00; UMCTL0=0xEF; /* uart0 8000000Hz 57595bps */ UCA0MCTL |= UCBRS_1 + UCBRF_0; // Modulation UCBRSx=1, UCBRFx= UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine** UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt and clock: //------------------------------------------------------------------------------------------ for (i = 0; i < 0xfffe; i++) // Delay for XTAL stabilization { }; // Setup ACLK UCSCTL5 |= DIVA_0; // ACLK= LFXT1CLK PJSEL |= BIT4+BIT5; // Port select XT1 //------------------------------------------------------------------------------------------ // Setup Clocks UCSCTL6 &= ~(XT1OFF); // XT1 On UCSCTL6 |= XCAP_3; // Internal load cap // Output ACLK to PJ3 pin 10 PJSEL |= BIT3; PJDIR |= BIT3; // Output SMCLK to PJ3 pin 10 PJSEL |= BIT0; PJDIR |= BIT0; // Loop until XT1 fault flag is cleared do { UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags } while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag UCSCTL3 = SELREF_0; // Set DCO FLL reference = XT1CLK UCSCTL4 |= SELA_0; // Set ACLK = REFO // Loop until XT1 fault flag is cleared do { UCSCTL7 &= ~XT1LFOFFG; // Clear XT1 fault flags } while (UCSCTL7&XT1LFOFFG); // Test XT1 fault flag // Initialize DCO to 2.45MHz __bis_SR_register(SCG0); // Disable the FLL control loop UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx UCSCTL1 = DCORSEL_6; // Set RSELx for DCO = 2.45 MHz UCSCTL2 = FLLD_1 | (((DCO_SPEED_HZ/ACLK_SPEED_HZ)) - 1); // Set DCO Multiplier for 2.45MHz // (N + 1) * FLLRef = Fdco // (74 + 1) * 32768 = 2.45MHz // Set FLL Div = fDCOCLK/2 __bic_SR_register(SCG0); // re-enable the FLL control loop // Worst-case settling time for the DCO when the DCO range bits have been // changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx // UG for optimization. // 32 x 32 x 2.45 MHz / 32,768 Hz = 76563 = MCLK cycles for DCO to settle __delay_cycles(400000); // Loop until XT1 & DCO fault flag is cleared do { UCSCTL7 &= ~(XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT1,DCO fault flags SFRIFG1 &= ~OFIFG; // Clear fault flags } while (SFRIFG1&OFIFG); // Test oscillator fault flag Any suggestions? Remark: with LPM0 and LPM1 it works Greets, Andi
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