Hi Prasanth, After a PUC, the Unified Clock System module default configuration is as follows: - MCLK is sourced from DCOCLKDIV (~1.048 MHz) - SMCLK is sourced from DCOCLKDIV (~1.048 MHz) - ACLK is sourced from XT1CLK (LF mode, which is XT1 at 32.768 kHz) When crystal startup is obtained and settled, the FLL stabilizes MCLK and SMCLK to 1.048576 MHz and fDCO = 2.097152 MHz. The UCS module can be configured or reconfigured by software at any time during program execution. This information came directly form Section 5.2 of the device user's guide, so please reference that document if you'd like to learn more about the different ways you can customize the UCS module. Thanks, Mitchell
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