After I reviewed the response from Mike Pridgen , I realized that I need to amend my previous response. The hardware entry sequence using the TEST and RESET pins will also trigger a BOR. In addition, it will set the SYSBSLIND bit inside the SYSCTL register where as other BOR that I mentioned earlier will clear that bit. However, this will not directly force a BSL. The TI factory programmed Flash memory has a routine somewhat like this: BSL_Protect: MOV.W #0, R12 ;default to invoke user reset BIS #SYSBSLPE+SYSBSLSIZE0+SYSBSLSIZE1, &SYSBSLC bit #SYSBSLIND, &SYSCTL jz BCC2BSL BIS.W #2,R12 ;change to invoke BSL instead BCC2BSL RETA It is this routine that indirectly made BSL entry sequence causes BSL. Had you modified this routine, you could make BOR always causes BSL (as TI Lady wishes) BSL_Protect: BIS #SYSBSLPE+SYSBSLSIZE0+SYSBSLSIZE1, &SYSBSLC MOV.W #2,R12 invoke BSL no mater what RETA
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