Antonio, It is important that the system is in VCORE1 and that the flash wait state is set to 1 in order for RevC to work at 48Mhz. It is entirely possible that the revision B silicon manifests a different issue when this part of the specification is violated. Please refer to sections 5.6 and 5.8 of the datasheet. www.ti.com/.../msp432p401r.pdf page 30 of revision r: www.ti.com/.../msp432p401r.pdf Best Regards, Chris
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