May I also participate? Look at SPI implementation on the CC3200 . It has some significant enhancements: - Selection of SPI word lengths at 8, 16, and 32 bits; - Multiple SPI word access with a channel using an enabled FIFO (up to 64 bytes); - No dead cycle between two successive words in slave mode. So, why do not implement this in a new generation of MSP432 (32-bit with FIFO) and MSP430 (16-bit with FIFO)? It will give a significant impact on overall performance characteristic when external SPI displays or DACs are used. But specially for DACs (where precise timings is essential) should be good to have additional trigger in SPI FIFO to send TX data controlled by an interrupt trigger from a timer. (In some DACs there is an additional data buffer with interrupt pin, so such specs for SPI are optional or useless for differential analog outputs). Thanks, Alexey
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