Part Number: MSP430FR2311 I have an MSP430FR2311 operating as an SPI slave. It is working correctly. My question is about how to properly handle error cases when the incoming master data is incorrect. Specifically, how to properly handle the case where the master only clocks out 7 bits during a chip-select cycle, when the MSP is configured for 8 bits. I have a test case where the master clocks out only 7 bits (an erroneous condition) during one chip-select cycle (STE is released after the seventh bit). The master then starts a new chip-select cycle and clocks out the correct number of bits (8) and I expect the byte value received by the MSP slave to be the value in that second set of 8 bits. What I'm seeing is the received value is a combination of the 7 bits from the first CS cycle, and the first bit from the second CS cycle. I understand why this is happening, the SPI slave state machine doesn't reset its shift register just because CS is de-asserted. The question I have is, what is the correct way to force the slave's state machine to reset so that in this second CS cycle the correct data is read? I have tried setting and then clearing the RST bit in the CTLW0 register (I don't have the exact register name handy here at home -- it's bit zero of the first SPI register) but that doesn't seem to work. When I do this, I don't get an SPI receive interrupt during the second CS cycle, where I expect to get one interrupt. Is this the right approach, or is there another way to reset the slave state machine?
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