[quote user="f. m."]It is the STM32F3 reference manual, named "DM00043574.pdf", document designated as RM0316.[/quote] Well, I do not see anything that would say that ST implemented other than AHB bus matrix. Not even sure which version. In contrast TI clearly told us that. What I see in ST doc is just bus matrix configuration information which is essentially "Table 6-37. Master and Slave Access Priority" in case of msp432. After all multi-master bus matrix is just multi-layer mux. Nothing much to implement differently than it is already done by ARM . [quote user="f. m."]And I still think TI could harmonize their documentation structure. Spatial distribution is no excuse.[/quote] Agreed :) TI shall clearly tell how bus and it's arbitration works in msp432. - Telling that bus used is AHB-Lite with only SINGLE transfer support is kinda obfuscated way to tell how it works. p.s. I am afraid that TI is not that focused on msp432, documentation is one of the proofs. Soon it will be 2 years since release of the msp432, but how many different chip variants are released since then?
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