Part Number: MSP430G2755 SLAU144J, pg. 358, 12.2.2 Starting the Timer, states: • When the timer mode is either up or up/down, the timer may be stopped by writing 0 to TACCR0. The timer may then be restarted by writing a nonzero value to TACCR0. In this scenario, the timer starts incrementing in the up direction from zero. How exactly does this happen? What is the linkage? Figure 12-1. Timer_A Block Diagram, pg 357, does not show any control lines between CCR0 and TAR control. I would like to see a block diagram that shows how CCR0 accomplishes this. ------------------------------- I know that CCR0 is "more special" than CCR1\CCR2... because it implied (not clearly stated why) in other text: 12.2.3.1 Up Mode, pg. 358 • The up mode is used if the timer period must be different from 0FFFFh counts. The timer repeatedly counts up to the value of compare register TACCR0, which defines the period, -- This makes sense because only one compare register can reset TAR, otherwise things would be a mess. 12.2.3.5 Up/Down Mode The up/down mode is used if the timer period must be different from 0FFFFh counts, and if a symmetrical pulse generation is needed. The timer repeatedly counts up to the value of compare register TACCR0 and back down to zero 12.2.6 Timer_A Interrupts Two interrupt vectors are associated with the 16-bit Timer_A module: • TACCR0 interrupt vector for TACCR0 CCIFG • TAIV interrupt vector for all other CCIFG flags and TAIFG There are several other references like this that indicate that CCR0 is "more special". ------------------------------- While this "special-ness" of CCR0 is implied, it is never actually explained. As I mentioned, I would really like to see a block diagram that shows how this linkage\control works and how it is different from the other CCRx's. Regards, Jim
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