//****************************************************************************** // MSP430FR5x9x Demo - eUSCI_A0, SPI 3-Wire Master Incremented Data // // Description: SPI master talks to SPI slave using 3-wire mode. Incrementing // data is sent by the master starting at 0x01. Received data is expected to // be same as the previous transmission TXData = RXData-1. // USCI RX ISR is used to handle communication with the CPU, normally in LPM0. // ACLK = 32.768kHz, MCLK = SMCLK = DCO ~1MHz. BRCLK = ACLK/2 // // // MSP430FR5994 // ----------------- // /|\ | XIN|- // | | | 32KHz Crystal // ---|RST XOUT|- // | | // | P2.0|-> Data Out (UCA0SIMO) // | | // | P2.1| Serial Clock Out (UCA0CLK) // // William Goh // Texas Instruments Inc. // October 2015 // Built with IAR Embedded Workbench V6.30 & Code Composer Studio V6.1 //****************************************************************************** #include volatile unsigned char RXData = 0; volatile unsigned char TXData; int main(void) { WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer // Configure GPIO P1SEL0 &= ~BIT5; // USCI_A0 SCLK pin P1SEL1 |= BIT5; P2SEL0 &= ~(BIT0 | BIT1); // USCI_A0 MOSI and MISO pin P2SEL1 |= BIT0 | BIT1; PJSEL0 |= BIT4 | BIT5; // For XT1 // Disable the GPIO power-on default high-impedance mode to activate // previously configured port settings PM5CTL0 &= ~LOCKLPM5; // XT1 Setup CSCTL0_H = CSKEY_H; // Unlock CS registers CSCTL1 = DCOFSEL_0; // Set DCO to 1MHz CSCTL2 = SELA__LFXTCLK | SELS__DCOCLK | SELM__DCOCLK; CSCTL3 = DIVA__1 | DIVS__1 | DIVM__1; // set all dividers CSCTL4 &= ~LFXTOFF; do { CSCTL5 &= ~LFXTOFFG; // Clear XT1 fault flag SFRIFG1 &= ~OFIFG; } while (SFRIFG1 & OFIFG); // Test oscillator fault flag CSCTL0_H = 0; // Lock CS registers // Configure USCI_A0 for SPI operation UCA0CTLW0 = UCSWRST; // **Put state machine in reset** UCA0CTLW0 |= UCMST | UCSYNC | UCCKPL | UCMSB; // 3-pin, 8-bit SPI master // Clock polarity high, MSB UCA0CTLW0 |= UCSSEL__ACLK; // ACLK UCA0BRW = 0x02; // /2 UCA0MCTLW = 0; // No modulation UCA0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine** UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt TXData = 0x1; // Holds TX data while(1) { UCA0IE |= UCTXIE; __bis_SR_register(LPM0_bits | GIE); // CPU off, enable interrupts __delay_cycles(2000); // Delay before next transmission TXData++; // Increment transmit data } } #if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__) #pragma vector=EUSCI_A0_VECTOR __interrupt void USCI_A0_ISR(void) #elif defined(__GNUC__) void __attribute__ ((interrupt(EUSCI_A0_VECTOR))) USCI_A0_ISR (void) #else #error Compiler not supported! #endif { switch(__even_in_range(UCA0IV, USCI_SPI_UCTXIFG)) { case USCI_NONE: break; case USCI_SPI_UCRXIFG: RXData = UCA0RXBUF; UCA0IFG &= ~UCRXIFG; __bic_SR_register_on_exit(LPM0_bits); // Wake up to setup next TX break; case USCI_SPI_UCTXIFG: UCA0TXBUF = TXData; // Transmit characters UCA0IE &= ~UCTXIE; break; default: break; } } I posted the link to this zipfile already, http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=SLAC710&fileType=zip
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