I am using following function to initialize system clock for msp430f5247 . It seems it got stuck in a second while loop as shown below. void Init_FLL(uint16_t fsystem, uint16_t ratio) { uint16_t d, dco_div_bits; uint16_t mode = 0; // Save actual state of FLL loop control, then disable it. This is needed to // prevent the FLL from acting as we are making fundamental modifications to // the clock setup. uint16_t srRegisterState = __get_SR_register() & SCG0; __bic_SR_register(SCG0); d = ratio; dco_div_bits = FLLD__2; // Have at least a divider of 2 if (fsystem > 16000) { d >>= 1 ; mode = 1; } else { fsystem 512) { dco_div_bits = dco_div_bits + FLLD0; // Set next higher div level d >>= 1; } UCSCTL0 = 0x0000; // Set DCO to lowest Tap UCSCTL2 &= ~(0x03FF); // Reset FN bits UCSCTL2 = dco_div_bits | (d - 1); if (fsystem <= 630) // fsystem < 0.63MHz UCSCTL1 = DCORSEL_0; else if (fsystem < 1250) // 0.63MHz < fsystem < 1.25MHz UCSCTL1 = DCORSEL_1; else if (fsystem < 2500) // 1.25MHz < fsystem < 2.5MHz UCSCTL1 = DCORSEL_2; else if (fsystem < 5000) // 2.5MHz < fsystem < 5MHz UCSCTL1 = DCORSEL_3; else if (fsystem < 10000) // 5MHz < fsystem < 10MHz UCSCTL1 = DCORSEL_4; else if (fsystem < 20000) // 10MHz < fsystem < 20MHz UCSCTL1 = DCORSEL_5; else if (fsystem < 40000) // 20MHz < fsystem < 40MHz UCSCTL1 = DCORSEL_6; else UCSCTL1 = DCORSEL_7; while (SFRIFG1 & OFIFG) { // Check OFIFG fault flag UCSCTL7 &= ~(DCOFFG+XT1LFOFFG+XT2OFFG); // Clear OSC flaut Flags SFRIFG1 &= ~OFIFG; // Clear OFIFG fault flag } if (mode == 1) { UCSCTL4 = (UCSCTL4 & ~(SELM_7 + SELS_7)) | (SELM__DCOCLK + SELS__DCOCLK); } else { UCSCTL4 = (UCSCTL4 & ~(SELM_7 + SELS_7)) | (SELM__DCOCLKDIV + SELS__DCOCLKDIV); } __bis_SR_register(srRegisterState); // Restore previous SCG0 } Please point out if I am doing anything wrong here. Same function works fine on msp430f5419a in our other boards. I was thinking that since both controller are from same family this should work as it is.
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