Hi Rolf, [quote user="Rolf Weber"]I'm looking for some settings or configuration that allows only one DMA transfer per rising Clock edge or per high level of DMAE0 [/quote] Unfortunately the DMAE0 can not be configured to trigger on edges instead it is configured for level trigger, in other words when DMAE0 reads a high level it will trigger the DMA transfer. So you will need to disable the DMA interrupt and wait until you read a low level on the DMAE0 pin before re-enable the next transfer. Having said that, I re-mapped the DMAE0 (P7.0) to P3.7 so I could use the GPIO falling edge interrupt to re-enable/configure my next DMA transfer and that seems to work correctly. My only concern is that we will not be able to meet the 1MHz timing. I measured that a single DMA transfer (16 bit) takes about 4us so you will be missing a few clocks and you still need to re-enable/configure the next DMA transfer. Instead of using the DMAE0 we could use the Timer A capture compare to trigger on both edges but even with this approach we will not be able to achieve the 1MHz timing. Hopefully this makes sense. Regards, David
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