See table "DCO Frequency" on p. 68 of the datasheet. For any one particular setting of the DCO, the tolerance is huge; for example, RSEL=5 and DCO=0 can result in any frequency between 2.5 and 6 MHz; that's 140 %. Due to these huge tolerances, the FLL searches for some setting that is nearest the desired frequency. The step between two DCO settings (S DCO ) is at most a ratio of 1.12. The modulator then can choose 32 steps between these two DCO settings, so the step between two modulator settings can be at most a ratio of about 1.0037, i.e., an error of about 0.37 %. (And if you rely on the clock to be stable, it's likely that you will get hurt by the jitter introduced by the modulator.)
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