Original I2C is only specified for 100kHz. The faster 400kHt mode requires 1) a slave supporting it and 2) more stringent bsu design. The 400kHz mode has different timing requirements for risning and falling signal edges which measn stronger pull-ups and less line capacitance. Also, there's indeed sort of a minimum ratio between SMCLK and fSCL (as the state machine reauires some clock cycles to properly handle the protocol and filter glitches). While the exact value of fSCL itself isn't critical (its a synchronous bus), it would be difficult to reliably run I2C with 250kHz when you only have 1MHz SMCLK, even though 4:1 is listed as minimum (8:1 in multi-master mode) and may work in ideal environment. If oyu don't know how to increase SMCLK, you shoudl read the clock system chapter of the users guide :)
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