Gents, the 150uA additional current and the fact that only a power cylce removes it sounds like the JTAG LDO is somehow turned on. This can happen on applicaiton level if a pulse between 1 ns and ~50us is applied unintentionally to the TEST pin. So do we have the layout avaialble to check the routing of the TEST pin? Is it possible that noise can somehow couple on this pin? A good cross check would be to pull test pin hard to GND via external 0Ohm connection as close as possible to the device pin. Another option to check if this is really the problem is to apply a 30us pulse to TEST pin to see if the LDO gets turned off. In such a case the current should go back. Maybe this is the more easy way to check if my assumption is right? By the way this behavior is a robustness weakness and not really a BUG or spec violation. Nevertheless this is fixed on Rev E because we want to improve the device performance also outside our spec! Best regards, Dietmar
↧