I have oversampling disabled, no modulation (UCAxMCTLW reg = 0) and set set the prescaler (UCAxBRW) appropriately based on the SMCLK rate. With oversampling disabled, section 22.3.9.1 is relevant for me and it says "In this mode, the maximum eUSCI_A baud rate is one-third the UART source clock frequency BRCLK." For me, BRCLK = SMCLK = 12MHz, so 4MBaud is the theoretical limit (though the datasheet for the RevB parts gives a max of 3MBaud with VCORE1). It would seem 2MBaud should be ok. I don't quite follow where your comment "If possible, use a clock that is an integer multiple of 8 times the bit rate" comes from, but I feel it is close to the core of this problem. There is some other limit in the relationship between BRCLK and the "BITCLK" (Baudrate) that I'm hitting up against when I run SMCLK = 12MHz. I think I'll continue on with SMCLK = 24MHz since that allows my clk to be at least 8 times the bit rate.
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