Sorry, "integer multiple of 8 times" is wrong; what matters is the ratio between BRCLK and the bit clock. With 24 MHz, the possible errors are half as big as those with 12 Mhz, but they are still there. See section 22.3.12 for how to calculate the receive bit timing errors. (In this case, there are no transmit bit timing errors because there is no modulation.) See the USCI UART Calculator if you don't want to do the calculations by hand.
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