Part Number: MSP432E401Y Hi, I'm trying to use the EPI of MSP432E401Y by Ti-RTOS. The EPI is used by a HOST-Bus 16bits mode. If there is a helpful sample register set value, please tell me. Thank you.
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Forum Post: MSP432E401Y: MSP432E401Y EPI Register Setting
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Forum Post: RE: MSP430F5529: MSP430F5529: mdio waveform looks not correct
Hi Eric, Just to understand your problem, you are trying to use USB-MDIO Software tool with MSP430 LaunchPad to connect to TI Phy and access extended registers. You are facing problem in this ? or you are trying to reverse engineer the software for your own implementation ? Regards, Geet
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Forum Post: RE: MSP432P401R: Voltage regulation for DVCC & AVCC of a MSP432P401R from a 6V-18V power input
Thomas, 1. The 200mA surge is not a condition that occurs in functional mode, so you don't need to consider this for purposes of Vdd variation while operating. That surge figure is from Table 5-19 of the MSP432P401 datasheet (Inrush current at startup). Designing for this 200mA in normal operating mode would be massively overdesign. 2. TI does not provide specific numbers in the datasheet for a given frequency of ripple on DVCC. I would refer you to the MSP432P401 datasheet (Table 5-30, Precision ADC Dynamic Parameters), which shows the Power supply rejection ratio (PSRR_AC), which is measured at 1kHz. 3. On _AVCC_ ripple at 500kHz, I would offer the same answer as (2) above in referring you to the PSRR_xx values for the impact of supply voltage ripple on the analog system. In general, the MSP432P4 LaunchPad power systems (decoupling caps) can be considered a good starting point for evaluation use. For achieving lowest noise on the analog systems, additional decoupling and/or separation of DVCC/AVCC may be needed, but the specifics will depend on your particular board design. The PSRR figures in the datasheet suggest that for "reasonable" input voltage ripple (a few %), the impact on the ADC will be quite small. The impact can be made even smaller (20x!) if using differential mode conversions. Hope that helps. This is all the information we can offer presently. Regards, - Bob L.
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Forum Post: RE: MSP-EXP430FR5969: MSP-EXP430FR5969
P2SEL1 |= BIT0 | BIT1; // USCI_A0 UART operation P2SEL0 &= ~(BIT0 | BIT1); Your code has mentioned above lines. But for MSP-EXP430FR5969 , RXD & TXD pins are 2.6 2.5, So i think the code should be as mentioned below Correct if iam wrong. P2SEL1 |= BIT5 | BIT6; // USCI_A0 UART operation P2SEL0 &= ~(BIT5 | BIT6); Also instead of checking for wrong data, iput check for the correct data and changed as follows if(RXData == TXData) // Check value { P1OUT |= BIT0; // If incorrect turn on P1.0 while(1); // Trap CPU } But still it is not working.
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Forum Post: RE: MSP-EXP430FR5969: MSP-EXP430FR5969
Thank you
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Forum Post: RE: MSP-EXP430FR5969: MSP-EXP430FR5969
There is no special hardware. I just have MSP-EXP430FR5969 development board connected to my PC and using Code Composer Studio.
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Forum Post: RE: MSP430F6736: MSP430F6736
Hi, before getting to your question please note that we recommend the MSP430F6736A for new designs. SLAA666 will give details on the differences between the MSP430F6736 and MSP430F6736A . Coming back to your posted question: The best starting point will be the Bootloader for MSP low-power microcontrollers web page. You'll find links to the different tools and an overview on programming the device. Besides, we also provide code examples for the MSP430F6736 . Those can be found in the TI Resource Explorer , just browse for your part, click on Software and check the different examples. Please let me know in case you have any follow-up questions after reviewing the material. Best regards, Britta
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Forum Post: RE: MSP-EXP430G2: Meaning of Buffering ACLK and other CLK configurations
Hi David, thanks for making us aware of the typo. I'll work on getting this changed to the correct output pin. Sorry for the confusion! Best regards, Britta
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Forum Post: RE: CCS/MSP432P401R: Having trouble sending ADC values through UART (probably baudrate calculation)
I'd guess that some bytes are missing. Instead of the constant values 0xAA and 0xBB, send the value of an increasing counter. The most likely reason is that the 24 MHz clock is not precise enough. A lower baud rate might help, or (if you are using the LaunchPad) synchronizing to one of the crystals.
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Forum Post: RE: CCS/MSP430G2231: SLAA604 files to modify for most recent compiler (MSP430G2231)
Hi Rob, I will need to check if I can provide the original files assuming that this might be tough. Let me come back to you on that. With regards to the error message: The message indicates that the object files are created using different compilers. Maybe you could have a look at that. Which compiler do you use? Thanks and best regards, Britta
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Forum Post: RE: CCS/MSP430F5359: LDO in msp430
Hi Karuna, did Clemens' answer help with what you need: If you have any other questions please let us know or otherwise please verify the given answer, Thanks and best regards, Britta
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Forum Post: CCS/MSP430FR5994: Program doesn't fit into available memory.
Part Number: MSP430FR5994 Tool/software: Code Composer Studio Hi, Following is the error which arises when I build my project. Program will not fit into available memory. Placement with alignment fails for section "RW_IPE" size 0xe8e6 lnk_ msp430fr5994 .cmd Here is the part where error arises. SECTIONS { GROUP(RW_IPE) { GROUP(READ_WRITE_MEMORY) { .TI.persistent : {} /* For #pragma persistent */ .cio : {} /* C I/O Buffer */ .sysmem : {} /* Dynamic memory allocation area */ } PALIGN(0x0400), RUN_START(fram_rw_start) GROUP(IPENCAPSULATED_MEMORY) { .ipestruct : {} /* IPE Data structure */ .ipe : {} /* IPE */ .ipe_const : {} /* IPE Protected constants */ .ipe:_isr : {} /* IPE ISRs */ } PALIGN(0x0400), RUN_START(fram_ipe_start) RUN_END(fram_ipe_end) RUN_END(fram_rx_start) } > 0x4000 .cinit : {} > FRAM /* Initialization tables */ .binit : {} > FRAM /* Boot-time Initialization tables */ .pinit : {} > FRAM /* C++ Constructor tables */ .init_array : {} > FRAM /* C++ Constructor tables */ .mspabi.exidx : {} > FRAM /* C++ Constructor tables */ .mspabi.extab : {} > FRAM /* C++ Constructor tables */ .text:_isr : {} > FRAM /* Code ISRs */ #ifndef __LARGE_DATA_MODEL__ .const : {} > FRAM /* Constant data */ #else .const : {} >> FRAM | FRAM2 /* Constant data */ #endif #ifndef __LARGE_CODE_MODEL__ .text : {} > FRAM /* Code */ #else .text : {} >> FRAM2 | FRAM /* Code */ #endif #ifdef __TI_COMPILER_VERSION__ #if __TI_COMPILER_VERSION__ >= 15009000 #ifndef __LARGE_CODE_MODEL__ .TI.ramfunc : {} load=FRAM, run=RAM, table(BINIT) #else .TI.ramfunc : {} load=FRAM | FRAM2, run=RAM, table(BINIT) #endif #endif #endif .jtagsignature : {} > JTAGSIGNATURE .bslsignature : {} > BSLSIGNATURE GROUP(SIGNATURE_SHAREDMEMORY) { .ipesignature : {} /* IPE Signature */ .jtagpassword : {} /* JTAG Password */ } > IPESIGNATURE .bss : {} > RAM /* Global & static vars */ .data : {} > RAM /* Global & static vars */ .TI.noinit : {} > RAM /* For #pragma noinit */ .stack : {} > RAM (HIGH) /* Software system stack */ .tinyram : {} > TINYRAM /* Tiny RAM */ /* MSP430 INFO memory segments */ .infoA : type = NOINIT{} > INFOA .infoB : type = NOINIT{} > INFOB .infoC : type = NOINIT{} > INFOC .infoD : type = NOINIT{} > INFOD .leaRAM : {} > LEARAM /* LEA RAM */ .leaStack : {} > LEASTACK (HIGH) /* LEA STACK */ /* MSP430 interrupt vectors */ .int00 : {} > INT00 .int01 : {} > INT01 .int02 : {} > INT02 .int03 : {} > INT03 .int04 : {} > INT04 .int05 : {} > INT05 .int06 : {} > INT06 .int07 : {} > INT07 .int08 : {} > INT08 .int09 : {} > INT09 .int10 : {} > INT10 .int11 : {} > INT11 .int12 : {} > INT12 .int13 : {} > INT13 .int14 : {} > INT14 .int15 : {} > INT15 .int16 : {} > INT16 .int17 : {} > INT17 LEA : { * ( .int18 ) } > INT18 type = VECT_INIT PORT8 : { * ( .int19 ) } > INT19 type = VECT_INIT PORT7 : { * ( .int20 ) } > INT20 type = VECT_INIT EUSCI_B3 : { * ( .int21 ) } > INT21 type = VECT_INIT EUSCI_B2 : { * ( .int22 ) } > INT22 type = VECT_INIT EUSCI_B1 : { * ( .int23 ) } > INT23 type = VECT_INIT EUSCI_A3 : { * ( .int24 ) } > INT24 type = VECT_INIT EUSCI_A2 : { * ( .int25 ) } > INT25 type = VECT_INIT PORT6 : { * ( .int26 ) } > INT26 type = VECT_INIT PORT5 : { * ( .int27 ) } > INT27 type = VECT_INIT TIMER4_A1 : { * ( .int28 ) } > INT28 type = VECT_INIT TIMER4_A0 : { * ( .int29 ) } > INT29 type = VECT_INIT AES256 : { * ( .int30 ) } > INT30 type = VECT_INIT RTC_C : { * ( .int31 ) } > INT31 type = VECT_INIT PORT4 : { * ( .int32 ) } > INT32 type = VECT_INIT PORT3 : { * ( .int33 ) } > INT33 type = VECT_INIT TIMER3_A1 : { * ( .int34 ) } > INT34 type = VECT_INIT TIMER3_A0 : { * ( .int35 ) } > INT35 type = VECT_INIT PORT2 : { * ( .int36 ) } > INT36 type = VECT_INIT TIMER2_A1 : { * ( .int37 ) } > INT37 type = VECT_INIT TIMER2_A0 : { * ( .int38 ) } > INT38 type = VECT_INIT PORT1 : { * ( .int39 ) } > INT39 type = VECT_INIT TIMER1_A1 : { * ( .int40 ) } > INT40 type = VECT_INIT TIMER1_A0 : { * ( .int41 ) } > INT41 type = VECT_INIT DMA : { * ( .int42 ) } > INT42 type = VECT_INIT EUSCI_A1 : { * ( .int43 ) } > INT43 type = VECT_INIT TIMER0_A1 : { * ( .int44 ) } > INT44 type = VECT_INIT TIMER0_A0 : { * ( .int45 ) } > INT45 type = VECT_INIT ADC12_B : { * ( .int46 ) } > INT46 type = VECT_INIT EUSCI_B0 : { * ( .int47 ) } > INT47 type = VECT_INIT EUSCI_A0 : { * ( .int48 ) } > INT48 type = VECT_INIT WDT : { * ( .int49 ) } > INT49 type = VECT_INIT TIMER0_B1 : { * ( .int50 ) } > INT50 type = VECT_INIT TIMER0_B0 : { * ( .int51 ) } > INT51 type = VECT_INIT COMP_E : { * ( .int52 ) } > INT52 type = VECT_INIT UNMI : { * ( .int53 ) } > INT53 type = VECT_INIT SYSNMI : { * ( .int54 ) } > INT54 type = VECT_INIT .reset : {} > RESET /* MSP430 reset vector */ } There are two loops which when I comment out, problem eradicates. But I'm not sure of how to fix this issue. I have deleted all the the printfs in my code.
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Forum Post: RE: CCS/MSP430G2553: with an external crystal source ; Timer A, Compare function for a 1 Hz toggle frequency
Holy moly, i have never thought that a blinking LED would ever fullfill me with such a joy! :D Thank you!
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Forum Post: RE: CCS/MSP430FR5949: JTAG issue, Error connecting to the target: The Debug Interface to the device has been secured
Hi Zrno, I am sure the BSL connection is OK since I get the BSL version back from the target. Still no idea why the MASS_ERASE gives an error message. Maybe a bug in the BSL-Scripter or the BSLof the target itself? As far as I understand is the BSL of the MSP430FR5949 in ROM so cannot be erased.
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Forum Post: RE: MSP430F5242: I2C Driverlib, repeated start condition
Here are the waveforms
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Forum Post: MSP-FET: MSP-FET Max Operating Temperating
Part Number: MSP-FET My question is rather, simple: what is the max operating temperature of the MSP-FET ? I attempted to find this information in one of the many technical documents, but it was to no success.
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Forum Post: RE: GRACE: The link to download the tool does not appear on the website
Hi Nicolas, this is odd as I am able to access the website just fine. Could you try a different browser? Best regards, Britta
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Forum Post: RE: EVM430-FR6047: DC Offset estimation
Hi Thibault, The release is scheduled to be sometime in the middle of the 4th quarter of this year. Thanks, Mitch
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Forum Post: RE: Compiler/MSP432E401Y: Lwip with uartecho functions
Hello Kalyan, It's not very clear what you are trying to achieve. Are you trying to send packets over UART to lwIP? What format are you planning to send the data to lwIP - HTTP, TCP or UDP? Are you trying to send lwIP packets to UART? What format are you planning to send the data to lwIP - HTTP, TCP or UDP? The "ethernet-based_io_control" example (in the folder "./examples/nortos/MSP_EXP432E401Y/lwip") does route text from a webpage (running over lwIP) to UART. Are you trying to do something else? Do you need to use lwIP? Another TCP/IP stack is also supported in SimpleLink MSP432E4 SDK which runs on RTOS. It is called NDK. There are some examples (like TCPecho and UDPecho), which can be modified to route data to UART instead of echoing to the source. These examples are in the folder "./examples/rtos/MSP_EXP432E401Y/ns". Thanks, Sai
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Forum Post: RE: MSP432P401R: MSP430 P/N recommendation to replace MSP432P401R on TIDEP-0091
I'm moving your post over to the Processors Forum (which owns the TIDEP-0091 TI Design). They would be better able to make specific recommendation. -Bob L.
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