Posting on behalf of our customer. I have run into an issue using the MSP430F247 UCB1 module in I2C mode. I am trying to interface to a TI LDC1314 via I2C and have hit a snag. Up until now I have had this working with the following configuration: MCLK = 12MHz DCO SMCLK = 12MHz / 4 = 3MHz I2C Clock Source = SMCLK SMCLK to SCL divider = 15 (200KHz) Sleeping in LPM1. When I startup I write the register address and the corresponding 16bit value for that register to the LDC. This is the process: Write UCTR and UCTXSTT to the UCB1CLT1 register and go to sleep. Interrupt fires-> write register address to UCB1TXBUF->exit ISR Interrupt fires-> write LSB to UCB1TXBUF->exit ISR Interrupt fires-> write MSB address to UCB1TXBUF->exit ISR Interrupt fires-> write UCTXSTP to UCB1CTL1 and clear UCB1TXIFG from UC1IFG->exit ISR All of this worked for the last couple of days until I realized that I needed to have SMCLK at 12MHz. So, I removed the DIVSx bit setting from BCSCTL2 (let SMCLK = 12MHz) and changed my divider for SMCLK to SCL from 15 to 60 (12MHz / 60 = 200kHz). I ran the code and noticed that just after sending the start bit the micro sets the SDA line high and then right back low before sending the I2C slave address. I don’t have control of this as once I set the UCTR and UCTXSTT bits the I2C module transmits the start bit and then the slave address and then checks for an ACK or a NACK. The interrupt is once the start condition is sent, while the slave address is being transmitted, I can load the first data byte into the output buffer to be transmitted once a successful ACK is received. Here is the scope picture of it working… blue is high when I am in the ISR: And here is it not working. All I changed is the source clock to the module and the divider from the source clock to SCL so that SCL stays at 200kHz. My MCLK is the same for both scenarios, 12MHz: As you can see the SDA line goes high and low with the higher SMCLK. This is causing something with the LDC to get screwed up and it doesn’t ACK it’s address. If I put SMCLK back to 3MHz and the divider back to 15 then it works again. I have looked through the errata sheet for the 247 and cannot find something that might explain this. Maybe you have an idea? Iam stuck on this and really need to get this project moving forward and I am at a place that I need help. Any help you can provide would be GREAT!! Regards, Mark
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