Update: I have slowed the SCL clock down to 50KHz and the ISR for the start condition being sent runs and exits before the glitch on SDA occurs. This rules out it having anything to do with the ISR. I did confirm that it doesn’t matter what the SCL clock is - it always starts ~135ns after SCL goes low (see second picture below) and is on for ~65ns. I also did this with SCLK at 12MHz and 6MHz with SCL at 200KHz and 50KHz (that is 4 combinations) and it is always 135ns after SCL goes low and always on 65ns. So.. I lowered MCLK to 8MHz and the times change to ~162ns after SCL goes low and high for 33ns. It appears to be dependent on MCLK and not SCLK which is the source clock for the SCL divider. The I2C state machine block diagram in the user manual doesn’t even have MCLK going anywhere. I have moved all my definitions and function calls from all over my project into a main.c file to mimic my exact code and call sequence. I have attached it to this email. I have compiled it and downloaded it to an F247 and ran it to verify it is doing the same thing I see on my board. Again, any help would be greatly appreciated.
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