Hi Martin, sorry for delay I had to work on some other things and also had to clarify how to communicate this behavior (in case my assumption is right). As mentioned in this post the flash alignment on our F5xx/F6xx is not explained in detail in the user's guide but I can tell you here that we have 32 bit flash interface on this 16 bit CPU architecture. Means we have a buffer in between to catch the 32 bits. In your case both loops are located within 5 words thats why alignment is not the problem you always need 3 flash access cycles. But the structure of the for loops explains it. And you did a great pre-work (hand written post) here analysing which loops were executed how often. Please see my picture below (red and blue marked locations represents a single flash access (32 bits)): For the 1s loop you have nearly the same number 2xflash access loops in relation to the 3xflash access loops which brings to overall power consumption a bit down. On the 0.5s loop you have a relation of ~1:11 (2xflash access loop vs. 3xflash_access loop) which brings overall consumption up. An easy test would be to make the 0.5s loop also 1s long and check in the disassembly if the excaclty the same loop executions will take place. Then repeat the current measurements. If you still see the difference it's something else. Best regards, Dietmar
↧