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Forum Post: MSP432 LaunchPad V2 with EDUMKII running Keil uvision V5.20 and MSPWare 3.40.00.25 no LCD output

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I've tried all the examples (except for Microphone FFT who’s code size was to big for Keil) and never see any output on the LCD. I've copied the LCD data to the Serial channel and see the applications seem to be working, just no LCD output. QUESTON 0: Have you used my hardware/software setup and did the LCD work? A Keil application for MSP432 LaunchPad seems to use a code skeleton of : startup_ msp432p401r _uvision.s //initialize the interrupt vectors & stack, call SystemInit, call _main system_ msp432p401r .c //contains SystemInit, sets vcoreX, waits, and mclk _main.c //any additional initialization and loop on application code Within SystemInit prior to updating the CS registers, CS->KEY is set to unlock the CS module. The __main for these LCD example applications update the clock before the application loop. QUESTION 1: Below in main I don’t see CS->KEY set, is this handled by the “MAP_CS_setDCOCenteredFrequency” and “MAP_CS_init_ClockSignal”? void main(void) { /* Halting WDT and disabling master interrupts */ MAP_WDT_A_holdTimer(); MAP_Interrupt_disableMaster(); /* Set the core voltage level to VCORE1 */ MAP_PCM_setCoreVoltageLevel(PCM_VCORE1); /* Set 2 flash wait states for Flash bank 0 and 1*/ MAP_FlashCtl_setWaitState(FLASH_BANK0, 2); MAP_FlashCtl_setWaitState(FLASH_BANK1, 2); /* Initializes Clock System */ MAP_CS_setDCOCenteredFrequency(CS_DCO_FREQUENCY_48); MAP_CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); MAP_CS_initClockSignal(CS_HSMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); MAP_CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1 ); MAP_CS_initClockSignal(CS_ACLK, CS_REFOCLK_SELECT, CS_CLOCK_DIVIDER_1); /* Initializes display */ Crystalfontz128x128_Init(); … more of _main Within Crystalfontz128x128_Init() the spi is configured eUSCI_SPI_MasterConfig config = { EUSCI_B_SPI_CLOCKSOURCE_SMCLK, LCD_SYSTEM_CLOCK_SPEED, LCD_SPI_CLOCK_SPEED, EUSCI_B_SPI_MSB_FIRST, EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT, EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW, EUSCI_B_SPI_3PIN }; LCD_SYSTEM_CLOCK_SPEED is defined as 48,000,000. LCD_SPI_CLOCK_SPEED is defined as 16,000,000 (1/3 of the system clock). The main above sets the DCO to 48MHz and 1 divisor for MCLK, HSMCLK, and SMCLK. QUESTION 2: Should this configuration work (with the __main clock init shown)? Shouldn’t the MCLK be running off HFXT 48MHz crystal, with SMCLK off DCO running at 16MHz? QUESTION 3: If this is true which of the two DCO ranges are recommended and what should be the value of Ndcotune (Kdcoconst and FCALcsdcoxrcal values)? Thank you for feedback, Morris

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