Hi Caleb, I review that piece of code and destination are properly write in DMA0DA register. Also, I change some settings of SHT, but I found something. It seems like ADC sets an additional ADCIFG after DMA interrupt is called, causing that DMA cycle starts again and temporal DMA0DA is updated with the previous destination address (array_1), So, although I update DMA0DA with the correct value (array_2), DMA cycle is already running using old temporal values, causing overlapping in buffers. This is the code for DMA and ADC: /* DMA */ DMACTL0 |= DMA0TSEL__ADC12IFG; /* ADC12IFG Trigger */ __data16_write_addr((unsigned short) &DMA0SA,(unsigned long) src); __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) dst); DMA0SZ = 32; DMA0CTL |= DMADT_4 | DMADSTINCR_3 | DMAEN | DMAIE; /* ADC */ ADC12CTL0 &= ~ADC12ENC; ADC12CTL0 |= ADC12ON | ADC12MSC; ADC12CTL1 |= (ADC12SHT01 ) | ADC12SHP | ADC12CONSEQ_2 | ADC12DIV1; // Repeat-single-channel ADC12CTL2 |= ADC12RES_2; //12-bits result ADC12CTL3 |= ADC12CSTARTADD_0 ; //Start in ADC12MEM0 ADC12MCTL0 |= ADC_CHANNEL_0 | ADC12VRSEL_1; // Channel 0 ADC input in MEM0; V_R+ = VREF and V_R- =AVSS uint8_t adc_opt_start_conv(){ uint8_t ret = 0x00; ADC12CTL0 |= ADC12ENC| ADC12SC; return ret; } uint8_t adc_opt_select_ch(uint8_t ch){ uint8_t ret = 0x00; ADC12CTL0 &= ~ADC12ENC; ADC12MCTL0 = 0; ADC12MCTL0 |= ch | ADC12VRSEL_1; // Channel x ADC input in MEM0; V_R+ = VREF and V_R- =AVSS return ret; } uint8_t dma_set_dst(uint16_t * dst){ __data16_write_addr((unsigned short) &DMA0DA,(unsigned long) dst); return ret; } DMA interrupt is something like: ADC12CTL1 &= ~(ADC12CONSEQ_2); ADC12CTL0 &= ~ADC12ENC; ... dma_set_dst(array_N); adc_opt_select_ch(N); adc_opt_start_conv();
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