Forum Post: XT2 / 3 frequency (50% duty cycle) on MSP430F5510 pin output

Few years ago my conclusion was that it is not possible to have frequency from XT2 (24 MHz) divided by 3 (8 MHz, 50% duty cycle) on ( MSP430F5510 ) port pin as output. Now, I am back to this topic again, and I am sure that this can't be done. Timers (50% duty cycle) / ACLK / SMCLK output can be XT2 divided by 2, 4, 8... not by 3. However, ADC10DIVx (ADC10CLK output) can be divided by 1, 2, 3, 4... and even in family datasheet ADC clock is presented as 50% duty cycle, it is not. On picture is (XT2 24 MHz) divided by 8, measured frequency is 3, but on logic analyzer it is not signal with 50% duty cycle.