Hi, I'm communicating between MSP430F5529 and a DS2482 (1-Wire <> I2C device). Normal bus transactions work fine when I issue a WRITE command and then repeated start and read command, as per the image below. BUT: When I issue a simple READ transaction on its own (as is required by the DS2482) without first writing, I get: A short pulse in the R/W slot No additional clock cycles to perform the read (its like as if the F5529 is expecting a write, not a read). Image below of problem: Code below to re-create the issue: //pre-clear any stale data u8Test = HWREG8(eBaseAddx + OFS_UCBxRXBUF); //Set the address of the slave with which the master will communicate. HWREG16(eBaseAddx + OFS_UCBxI2CSA) = u8DeviceAddx; //Set USCI in Receive mode HWREG8(eBaseAddx + OFS_UCBxCTL1) &= ~UCTR; //Send start condition. HWREG8(eBaseAddx + OFS_UCBxCTL1) |= UCTR + UCTXSTT; //after the start condition is set, the device will tx the pre-loaded address, with the Rx bit //wait for the start bit to be done, this occurs if the slave acks u8Test = u8MSP430_I2C_WAIT__StartBit(eBaseAddx); if(u8Test == 0U) { //ERROR: Rx buffer is never full because module does not send second set of clock cycles. //u8Test = u8MSP430_I2C_WAIT__RxBufferFull(eBaseAddx); u8Test = 0U; if(u8Test == 0U) { //Send stop condition, must be done early due to errata HWREG8(eBaseAddx + OFS_UCBxCTL1) |= UCTXSTP; //Capture data from receive buffer after setting stop bit due to MSP430 I2C critical timing. *pu8Byte = HWREG8(eBaseAddx + OFS_UCBxRXBUF); s16Return = 0; } else { //slave not acked s16Return = -33; } } else { //no slave ACK s16Return = -10; } Can anyone please help!. I know there is quite a bit of errata on the I2C module in F5529, but this issue does not appear. Thanks Stomp!.
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