Our system has 2 processors. The master processor is able to boot TI C5535eZdsp through UART. However, the C5535eZdsp bootloader sets up to receive data at UART baud rate of 57600. Loading DSP FW takes about 30 seconds. We need to decrease the loading time to less than 10 seconds. My questions are: My UART boot experiment was done through C5535eZdsp board. When we use C5535 DSP to build our own application board, the system clock will be 16.384 MHz. Based on below C5535 DSP on-chip bootloader document: • CPU Clock setup – If CLK_SEL = 0, the bootloader powers up the PLL and sets its output frequency to 12.288 MHz (multiply 32 768 Hz RTC Clock by 375). – If CLK_SEL = 1, the bootloader bypasses the PLL and uses CLKIN. Note that CLKIN is expected to be 11.2896 MHz, 12.0 MHz, or 12.288 MHz. Then on our board the bootloader baud rate will be 57600 * 16.384 / 12 = 78643. Is my calculation correct? 2. Besides changing DSP CLKIN frequency, is there other way to increase C5535 bootloader UART baud rate? We cannot modify C5535 on-chip bootloader. However, if some other SW / HW setting affect the baud rate, we may be able to change the setting to increase the UART baud rate. For example C5535 bootloader document (sprabl7a.pdf) tells us: To use UART boot, the ezdsp5535 board DIP SW3 should be set to CLK_SEL = OFF and UART_BUFF_EN = ON. Do you know what is the differences to set UART_BUFF_EN = ON or OFF? 3. My last choice is writing a “fast UART boot loader” to decrease the UART loading (DSP FW) time. That is first let the C5535 on-chip bootloader to load “fast UART boot loader”. Then let the “fast UART boot loader” run to load DSP FW. If TI support can provide “C5535 on-chip bootloader source code”, that will be great. If anyone can provide similar UART receiving source code, reference document or suggestions, that will also help me a lot. I highly appreciate. Thanks! Jun
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