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Forum Post: RE: SPI communication Between MSP430F5529LP

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To insert code so that it is readable, use the "Insert Code" button. There is a problem in this line: while (!(UCB0IFG&UCTXIFG)) ; //hold until transmit finish The comment is wrong; the TXIFG bit indicates that the TXBUF register is empty, which happens immediately after the byte has been moved from TXBUF to the internal shift register. To wait until the actual transmission has finished, check the UCBUSY status bit. Or, in the case of SPI, wait until the module has read the byte from the MISO line, i.e., check RXIFG.

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