Hi, I was setting up a little test, where the dma uses the TimerA1 as Trigger. The idea is that the timer generates an output CLK (PMAP P7.0 to TA1.3) and also Triggers the DMA (TA1.2 = Channel 3) that writes its Data to a parralel Port PB (P3 and P4). When the DMA is finished, the dma ISR stops the dma and enables the Timer ISR for one last clock cycle. Afterwards also the Timer is stopped. The general setup is working with frequencies KEYID = PMAP_KEYID_VAL; PMAP->CTL |= PMAP_CTL_PRECFG; P7MAP->PMAP_REGISTER0 = PMAP_TA1CCR3A; PMAP->KEYID = 0; _UNLOCK_INT //enable Parallel BUS DMA //Channel 3 TimerA1 CCR2 uint8_t controlTable[256]; /* Configuring DMA module */ MAP_DMA_enableModule(); MAP_DMA_setControlBase(controlTable); MAP_DMA_assignChannel(DMA_CH3_TIMERA1CCR2); // stop DMA CH5 MAP_DMA_disableChannel(3); // compute and set divider for SMCLK in up mode for 100KHz output TA1CCR0 = dcModClock::sm_ulSMClkFrequency / 300000ul - 1; //CCR0 creates base frequency TA1CCR2 = TA1CCR0 / 10; // DMA Transfer enable at the beginning of the timer intervall TA1CCR3 = TA1CCR0 / 2; // set at half, reset at end // use set/reset output mode but wait for global enable TA1CCTL3 = OUTMOD_3; // set/reset // enable TA1.3 clock timer function for P7.0 P7SEL0 |= 0x01; P7SEL1 &= ~0x01; P7DIR |= 0x01; // output unsigned short t_usSampleSize=8; unsigned short t_usSampleData[t_usSampleSize]; unsigned short t_usCount=0; for(t_usCount=0;t_usCount INT0_CLRFLG |= 0x08; MAP_DMA_clearInterruptFlag(3); _nop(); // program and start TA0 TA1CTL = TASSEL__SMCLK + // SMCLK as timer clock (always active) ID__1 + // input divider 1 MC__UP; // timer in up mode } /** * interrupt service Routine for DMA transfer finish */ void dcSA32ConverterHub::DMA_INT1_ISR( void ) { // clear IFG // MAP_DMA_clearInterruptFlag(3); DMA_Channel->INT0_CLRFLG |= 0x08; MAP_DMA_disableChannel(3); MAP_DMA_disableInterrupt(INT_DMA_INT1); TA1CCTL0 &= ~TAIFG; //clear timer interupt flag TA1CTL &= ~CCIFG; //clear timer interupt flag TA1CTL|= TAIE;//enable general Timer Interupt TA1CCTL0 |=CCIE;//enableTimer Chanel 1 Interupt } /** * interrupt service routine (tx/tx) registered at NVIC */ void dcSA32ConverterHub::INT_TA1_0_ISR( void ) { TA1CTL &= ~TAIE;//disable next Timer Interupt TA1CCTL0 &= ~CCIE;//Timer Chanel 0 disable TA1CTL = MC__STOP; //stop timer TA1CTL = TACLR;// clear timer TA1CCTL0 &= ~TAIFG; //clear timer interupt TA1CCTL2 &= ~TAIFG; //clear DMA Timer Trigger interupt TA1CTL &= ~CCIFG; //clear timer interupt //deselect Timer Out Function on Port 7.0 P7SEL0 &= ~0x01; P7SEL1 &= ~0x01; P7OUT &= ~0x01; // low P7DIR &= ~0x01; // input //set Parallel Port to input low again PBOUT = 0x0000; PBDIR = 0x0000; } Within the Code i change two parameters, one for the amount of Data to be transfered (eg. 8,10,12) unsigned short t_usSampleSize=8; and also the sampling frequency (here for 300KHz) TA1CCR0 = dcModClock::sm_ulSMClkFrequency / 300000ul - 1; //CCR0 creates base frequency, SMCLK = 24MHz I also add some screenshots,of what i've observed. Channel 1 is the Output CLK created by the TimerA1, CH2 is the LSB of the parallel Port which toggles on every clk cycle. in some cases the last data output is delayed and additional CLK cycles are created (e.g 200KHz 10 Datatransfers). changing the amount of Data transfers also changes the DMA ISR Latency, so it can work (e.g 200KHz 12transfers). Those measurement are repeatable,and the latency is somehow connected to the amount of data transfered. It rather seems that the DMA ISR is triggered to certain low frequent timeslot, then to an actuall finish event. here are some screenshots (sorry for the bad quality) 200Khz 10 transfers (failed) 200Khz 12 transfers (ok) 300Khz 8 transfers (failed) 300Khz 10 transfers (failed) 300Khz 12 transfers (ok) p.s. Moving the Timer ISR Code into the DMA ISR, doesnt change the latency at all. It only cuts the last CLK.
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